IEEE Transactions on Very Large Scale Integration (VLSI) Systems : Impact Factor & More
eISSN: 1557-9999pISSN: 1063-8210
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Key Metrics
CiteScore 
5.9
Impact Factor
< 5
SJR
Q2Software
SNIP
1.47
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Topics Covered on IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Journal Specifications
Indexed in the following public directories
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Scopus 
Inspec 
SJR
| Overview | |
| Publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC |
| Language | English |
| Frequency | Monthly |
| General Details |
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Recently Published Papers in IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Table of Contents
- 1 Feb 2026
- IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ASTRA: Automated Insertion of Distributed Entropy Sources for Robust Authentication
- 1 Feb 2026
- IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A 0.67–5.67-GHz Ring-Based MDLL With 154-fs RMS Jitter and Stochastic Sampling for Spurious Tone Reduction in 5-nm FinFET
- 1 Jan 2026
- IEEE Transactions on Very Large Scale Integration (VLSI) Systems
HFMLLR: Heterogeneous Feature Mining for Low-Overhead Latency Reduction Scheme of LDPC Codes in 3-D TLC nand Flash Memory
- 1 Jan 2026
- IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Self-Calibrating Analog Circuitry for Softmax-Scaled Function With Analog Computing-In-Memory
- 1 Jan 2026
- IEEE Transactions on Very Large Scale Integration (VLSI) Systems
AccLLM: Accelerating Long-Context LLM Inference via Algorithm-Hardware Co-Design
- 1 Jan 2026
- IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Table of Contents
- 1 Feb 2026
- IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ASTRA: Automated Insertion of Distributed Entropy Sources for Robust Authentication
- 1 Feb 2026
- IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A 0.67–5.67-GHz Ring-Based MDLL With 154-fs RMS Jitter and Stochastic Sampling for Spurious Tone Reduction in 5-nm FinFET
- 1 Jan 2026
- IEEE Transactions on Very Large Scale Integration (VLSI) Systems
HFMLLR: Heterogeneous Feature Mining for Low-Overhead Latency Reduction Scheme of LDPC Codes in 3-D TLC nand Flash Memory
- 1 Jan 2026
- IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Self-Calibrating Analog Circuitry for Softmax-Scaled Function With Analog Computing-In-Memory
- 1 Jan 2026
- IEEE Transactions on Very Large Scale Integration (VLSI) Systems
AccLLM: Accelerating Long-Context LLM Inference via Algorithm-Hardware Co-Design
- 1 Jan 2026
- IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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