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eISSN: 1557-9999pISSN: 1063-8210
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems Key Metrics
CiteScore 
5.9
Impact Factor
< 5
SJR
Q2Software
SNIP
1.47
Topics Covered on IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Journal Specifications
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SJR
| Overview | |
| Publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC |
| Language | English |
| Frequency | Monthly |
| General Details |
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Recently Published Papers in IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A 1-MS/s 64-Channel Data Acquisition System With Full-Scale Input Range for Area-Sensitive Application Achieved 165.3-dB FoM<sub>S</sub>/Ch
- 1 Jun 2025
- IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Publication Information
- 1 May 2025
- IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Two-Stage CMOS Amplifier With High Degree of Stability for All Capacitive Loads
- 1 May 2025
- IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Charge Domain SRAM Computing-in-Memory Macro With Quantized Interval-Optimized ADC and Input Bit-Level Sparsity-Optimized P2O-DAC for 8-b MAC Operation
- 1 May 2025
- IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Society Information
- 1 May 2025
- IEEE Transactions on Very Large Scale Integration (VLSI) Systems
High Signal-to-Noise Ratio and High-Sensitivity 4-D LiDAR Imaging Receiver
- 1 May 2025
- IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A 1-MS/s 64-Channel Data Acquisition System With Full-Scale Input Range for Area-Sensitive Application Achieved 165.3-dB FoM<sub>S</sub>/Ch
- 1 Jun 2025
- IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Publication Information
- 1 May 2025
- IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Two-Stage CMOS Amplifier With High Degree of Stability for All Capacitive Loads
- 1 May 2025
- IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Charge Domain SRAM Computing-in-Memory Macro With Quantized Interval-Optimized ADC and Input Bit-Level Sparsity-Optimized P2O-DAC for 8-b MAC Operation
- 1 May 2025
- IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems Society Information
- 1 May 2025
- IEEE Transactions on Very Large Scale Integration (VLSI) Systems
High Signal-to-Noise Ratio and High-Sensitivity 4-D LiDAR Imaging Receiver
- 1 May 2025
- IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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